1. Field of the Invention
The present invention relates to a metal semiconductor field-effect transistor used for power amplification and a method of fabricating the same.
2. Description of Related Art
Generally, metal semiconductor field-effect transistors (MESFET) for power amplifier use are required to have a large gate-drain breakdown voltage and a small drain conductance for operation under large signals. One previous approach to improving the gate-drain breakdown voltage capability is the so-called offset gate configuration in which the gate electrode is formed nearer to the source, or in other words, by spacing the gate farther away from the drain.
FIG. 1 is a cross sectional view cutting across the source, drain, and gate regions formed alternately in interlaced fashion in a prior art MES field-effect transistor employing the offset gate configuration. In the figure, the reference numeral 1 designates a semiconductive GaAs substrate. In the surface of the GaAs substrate 1, a drain region of n.sup.+ conductivity type (a high-impurity concentration active layer forming the drain) 5 and a source region of the same n.sup.+ conductivity type (a high-impurity concentration active layer forming the source) 6, separated from each other by a prescribed distance, are formed to a prescribed depth from the surface of the GaAs substrate 1, whereas between the drain region 5 and the source region 6, there is formed a channel layer 4 of n conductivity type to a depth shallower than the drain and source regions 5 and 6.
On the surface of the GaAs substrate, there are formed a drain electrode 9 and a source electrode 10 corresponding respectively to the drain region 5 and the source region 6, between which is formed a gate electrode 11 electrically isolated from adjacent areas by a SiN film 2 and a SiO.sub.2 film 8 and connected to the channel layer 4. The gate electrode 11 takes the so-called offset gate configuration so that the gate electrode 11 is formed nearer to the source region 6 than to the drain region 5.
However, in the prior art MES field-effect transistor, the enlarged gate-to-drain spacing inevitably leads to an increase in the drain resistance, which causes such problems as degradation in field-effect transistor characteristics such as mutual conductance and drain current and an inability to effectively reduce the drain conductance.
FIG. 2 is a graph showing the drain voltage (source-drain voltage) Vd-drain current (source-drain current) Id characteristic of the prior art MES field-effect transistor (gate length 0.9 .mu.m, gate width 100 .mu.m), the drain voltage Vd (V) being plotted along the abscissa and the drain current Id (mA) along the ordinate. It can be seen from the graph that, in the region where the drain voltage Vd exceeds 5.0 (V), the drain current Id abruptly increases, which means an increase in the drain conductance; therefore, the static characteristic of the transistor is not satisfactory.
FIG. 3 is a graph showing the gate voltage Vg-drain current Id-mutual conductance gm characteristic of the prior art MES field-effect transistor, the gate voltage Vg (V) being plotted along the abscissa and the drain current Id (mA) and mutual conductance gm (mS) along the ordinate. As is apparent from the graph, the mutual conductance gm is low for the positive region of the gate voltage.
FIG. 4 is a graph showing the gate-drain reverse current-voltage characteristic of the prior art MES field-effect transistor, the gate-drain reverse voltage Vrgd (V) being plotted along the abscissa and the gate-drain reverse current Irgd (A) along the ordinate. As the graph shows, for Vrgd at around 14 (V), the gate-drain reverse current already reaches 10.sup.-5 (A) which is generally considered as the gate-drain breakdown voltage limit.